意得法论坛 - Radar and Sensors - Power By Team Board 标题: Radar and Sensors     [打印本页]
来自: 意得法论坛 - 军事航空航天
链接: http://www.wetech-ic.com/bbs/teams//Thread.asp?tid=571

作者: jony     时间: 2010-07-08 9:40:11     标题: Radar and Sensors

Modern warfare in urban and mountainous environments depends heavily upon situational awareness. Combat personnel in the air, at sea, and on the ground need to monitor their surrounding environments and identify threats as soon as possible. State-of-the-art military sensors must process vast amounts of data to provide “actionable intelligence” as rapidly as possible. This requires high processing rates (in GMACS and GFLOPs), high-speed transceivers for system bandwidth, power vs. performance design flexibility, and a robust design flow to meet modern weapon system demands.

High-speed signal processing is critical to the function of advanced sensor systems. To meet the demands of radar and sensor system designs, Altera offers digital signal processing (DSP) power in its high-density Stratix® series FPGAs and HardCopy® series ASICs.

 

Figure 1. Sensor Array Block Diagram

Altera's 28-nm Stratix V FPGAs can address the unique design requirements of radar and advanced sensor technologies. With 825-Gbps full-duplex serial transceiver bandwidth, large DSP counts, excellent signal integrity, highly scalable embedded processing blocks, and logic density leadership up to 1,100K logic elements (LEs), Stratix V FPGAs offer true system-on-programmable-chip (SOPC) possibilities for military sensor designs.

Stratix V FPGAs provide the following advantages for radar and sensor applications:

Figure 2. Variable-Precision DSP Block Architectures 

Figure 2. Variable Precision DSP Block Architectures 
Figure 2. Variable Precision DSP Block Architectures 

Prototype on FPGA, Ship on ASIC

With 28-nm HardCopy V ASICs with high-speed transceivers, you have more options for high-speed logic. Design, prototype, and test using Stratix V transceiver FPGAs. When you're ready for production, migrate your design to HardCopy V transceiver ASICs. HardCopy V ASICs can reduce power by up to 50 percent, increase  performance, and enhance SEU immunity in your system. Transitioning from FPGA to ASIC, using Altera’s design flow, costs less than 20 percent of traditional ASIC design and requires no additional design tools outside of Quartus® II software.

Related Links



Powered by Team Board